1 Introduction
The main content of this paper is to use Ethernet technology to build an embedded Web2Se ve r with DSP as the core and interconnect with Intenet to realize status monitoring, fault detection, data collection, energy scheduling and distribution of the photovoltaic system. , Measurement, etc.
2 System realization principle
Figure 1 is a system block diagram of a photovoltaic power generation monitoring system. The most important part is the embedded Web2seve r with DSP as the core, electric energy measurement and related parameter monitoring, LCD display and other parts. Among them, the electric energy measurement part should not only measure the electric energy and harmonic amount converted by the inverter, but also collect solar sensor information to monitor solar radiation, solar panel temperature, solar cell array voltage, Battery voltage, solar cell array current, battery current. Therefore, it is no longer a traditional electrical energy measurement, but a fully functional data acquisition system. Therefore, advanced DSP measurement technology is adopted to ensure high accuracy and high stability of the energy meter.
3 System design
3. 1 choice of communication method
This system adopts the communication method of Ethernet. Its advantages are that the Ethernet is widely used, the cost is low, the communication rate is high, and the hardware and software resources are very rich. Due to these advantages of Ethernet, there are many ways to use Ethernet technology as a network communication platform. Advantages, through Intenet access system, as long as you have a computer, PDA or mobile phone with Internet access, you can automatically monitor the equipment in the photovoltaic system anytime and anywhere, and optimize the management and control of energy. Application prospects.
3. 2 The design of network communication module based on ADSP2BF537
This system selects ADSP2BF537 as the main controller. The chip is a high-performance blackfin processor with a clock frequency of up to 600MHZ. It has 132KB full-speed SRAM on-chip, 10-stage R ISC MCU / DSP pipeline, and has the best code density. 32-bit ISA, powerful and flexible cache is very suitable for soft real-time control and industry standard systems, as well as hard real-time signal processing, and the chip is embedded in IEEE802. 3 compatible 10/100 Ethernet MAC, with a buffer oscillator output to A separate PHY is very suitable as an Ethernet controller, which simplifies the circuit design and saves design costs. The physical layer interface chip selects LAN83C185. The LAN83C185 chip is a low-power high-integration analog interface IC, including an encoder / decoder, scrambler / descrambler, transmitter with shaping and output driver, and chip Twisted pair receiver with internal adaptive equalizer and baseline roaming (BLW) correction, clock and data recovery circuit and media separate interface (M II) section, integrated DSP with adaptive equalizer, supports automatic circulation and parallel detection , Working voltage 3. 3V, fully compatible with IEEE 802.12 / 802 / 3u standard, with full-duplex 10BASE2T / 100BASE2TX transceiver, supporting 10Mbps and 100Mbps unshielded twisted pair, complete power management features
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