**Abstract**: The traditional interpolation algorithm struggles with maintaining image details when scaling video images, especially when producing high-resolution outputs. To address this, a multi-phase interpolation algorithm is employed for video image scaling. This paper mainly describes the algorithm's principle and its corresponding hardware architecture. The system uses Xilinx Spartan6 series FPGA to control the hardware circuit. It supports real-time video signal processing from four-channel cameras, displaying the output at a resolution of 1920x1080@60 Hz. The results demonstrate that the system maintains good detail preservation while ensuring real-time performance.
**1. Preface**
Video image scaling, also known as resolution conversion or resampling, is a crucial technology in digital video processing. It directly impacts the quality of the output video and the overall visual experience. Today, it is widely used in fields such as medical imaging, engineering, multimedia, and video conferencing. Traditional algorithms like nearest neighbor, bilinear, and bicubic interpolation have limitations, particularly in preserving fine details during scaling. These methods can introduce aliasing, especially when dealing with high-resolution outputs. In contrast, the multi-phase interpolation algorithm offers better detail retention and is widely adopted in industry applications.
**2. Algorithm Principle**
The basic idea of video image scaling is to map an original image of size (M, N) to a target image of size (X, Y). Mathematically, this involves determining the pixel value of the output image based on the input pixels through a function:
Pixelout(x, y) = f(i, j, Pixelin(i, j)).
The multi-phase interpolation method enhances this process by considering the spatial correlation between pixels. The general approach involves two-dimensional filtering, which can be expressed as:
Pixelout(x, y) = ∑_{i=0}^{HTaps-1} ∑_{j=0}^{VTaps-1} Pixelin(x - HTaps/2 + i, y - VTaps/2 + j) × Coef(i, j).
To simplify computation, the two-dimensional filter is often split into two one-dimensional filters, reducing the number of multipliers and computational load. This makes the algorithm highly suitable for real-time hardware implementations, such as those using FPGAs.
**3. System Hardware Structure**
The system architecture is shown in Figure 1. It utilizes Xilinx Spartan6 series FPGA to implement the multi-phase interpolation algorithm. Four analog cameras provide the input video signals, which are converted to digital format using the TW2867 video decoder chip. The FPGA processes the data, storing it in DDR3 memory to ensure synchronization between input and output rates. After scaling, the output signal is encoded by the SIL9134 chip and transmitted via HDMI for display. This setup ensures high-quality video output with minimal latency.
**3.1 Related Chip Introduction**
**3.1.1 Video Decoder Chip**
The TW2867 is a multi-channel video decoder that converts analog video signals into digital format. It supports multiple video standards and provides reliable data transmission to the FPGA for further processing. Its integration ensures smooth video capture and preprocessing, forming the foundation of the entire system.
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