**Abstract**: Traditional interpolation algorithms often struggle with maintaining image details when scaling video images, especially when producing high-resolution outputs. To address this issue, a multi-phase interpolation algorithm is employed for video image scaling. This paper explains the algorithm's principle and its corresponding hardware architecture. The control logic of the system is implemented using Xilinx Spartan6 series FPGA. The system can receive video signals from four channels and display them at a resolution of 1920x1080@60 Hz. The results demonstrate that the system achieves real-time performance while preserving image details effectively.
**1. Introduction**
Video image scaling, also known as resolution conversion or resampling, is a crucial technology in digital video processing. It directly impacts the quality and visual experience of the output video. Today, this technology is widely applied in fields such as medical imaging, engineering, multimedia, and video conferencing.
Traditional scaling methods include nearest neighbor, bilinear, and bicubic interpolation. Other techniques like edge-based, B-spline, and adaptive interpolation are also used. However, these methods may introduce aliasing artifacts, especially when dealing with high-resolution videos, leading to poor detail preservation. In contrast, multi-phase interpolation offers better detail retention and is commonly used in industry due to its superior performance.
**2. Algorithm Principle**
The basic idea of video image scaling is to convert an input image of size (M, N) into a target image of size (X, Y). Mathematically, this can be expressed as:
Pixelout(x, y) = f(i, j, Pixelin(i, j)), where i, j represent coordinates of the original image, and x, y are the coordinates of the target image.
The process involves mapping pixel values from the source to the destination using a mathematical relationship. A typical two-dimensional filtering approach is used, which can be represented as:
Pixelout(x, y) = ∑∑Pixelin(...) × Coef(...).
To simplify the operation, the two-dimensional filter is often split into horizontal and vertical one-dimensional filters. This reduces the number of multiplications required and improves real-time performance, making it ideal for hardware implementation.
**3. System Hardware Structure**
The system architecture is shown in Figure 1. It uses a Xilinx Spartan6 FPGA to implement the multi-phase interpolation algorithm. Four analog cameras provide the input video signal, which is converted to digital format by the TW2867 video decoder chip. The data is then processed by the FPGA, stored in DDR3 memory, and scaled before being output via HDMI. The final video signal is encoded by the SIL9134 chip and displayed on a screen.
**3.1 Related Chip Introduction**
**3.1.1 Video Decoder Chip**
The TW2867 is a multi-channel video decoder that converts analog signals into digital format, ensuring compatibility with the FPGA processing unit. It supports multiple video standards and provides reliable input for the scaling system.
**3.1.2 FPGA Device**
The Xilinx Spartan6 FPGA is chosen for its low power consumption and high performance. It enables efficient execution of complex scaling algorithms, supporting real-time video processing.
**3.1.3 DDR3 Memory**
DDR3 memory is used to buffer the incoming video data, allowing for synchronized read and write operations during the scaling process. This ensures smooth and continuous video output.
**3.1.4 HDMI Encoder**
The SIL9134 encoder is responsible for converting the scaled video data into an HDMI-compatible signal, which is then sent to the display for viewing.
This system demonstrates the practical application of multi-phase interpolation in real-time video scaling, offering both high-quality image output and efficient hardware utilization.
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