The new USB type-c connector with forward and reverse plug-in guarantees the user the trouble of plugging in a USB device - regardless of how the plug is plugged in, the connection should work effectively.
The USB type-c also supports the following technologies: USB 3.1 specification with data rates up to 10 Gbit/s, power output up to 100 W, audio multiplexing, and switching modes for processing video signals such as DisplayPort or MHL.
So it's no surprise that hundreds of vendors are rolling out products that support USB type-c. In fact, more than 100 suppliers from many areas, from connecting cables to laptops, participated in the first USB type-c interoperability test in July 2015 to test their products and prototypes. Interoperability was tested.
Although the industry has been dealing with USB for decades, implementing Type-C connectivity still brings many new challenges. For example, when operating at a data rate of 10 Gbit/s, the voltage swing on the data line is below 0.5V. The designer needs to implement an equalizer in the physical layer (PHY) connected to the receiving end to obtain the input signal. At this time, the "eye" in the eye diagram of the signal is basically closed, and the necessary equalization needs to be implemented to make the signal eye diagram. The "eyes" in the opening are open, and at the same time, the display signal represents logic 0 or logic 1.
There are still many other challenges when implementing Type-C connections, especially when the USB 3.1 specification works at full data rates of 10 Gbit/s.
Rethink PHY
For example, the forward and reverse plug-in nature of a connector requires reconfiguration of the physical layer in the implementation. When running at a USB 2.0 data rate, the designer can use a pair of resistors to short-circuit the two data paths into the physical layer to indicate how the connector is plugged in. At lower USB 2.0 data rates, the physical layer has enough performance margin to handle the reflections caused by shorted data paths.
For USB 3.0 and 3.1 data rates, designers need to implement two data paths to handle higher rates. With one connector in one direction, the system is connected to one data path, while in the other direction, the system is connected to another data path. A dual data path is necessary because when transmitting at 5 Gbit/s and 10 Gbit/s data rates, singularity by shorting the data path will cause too much signal reflection, which will decompose the data.
The designer needs to decide how to solve this problem. One solution is to use two physical layers with one physical layer in each direction. The disadvantage of the dual physical layer solution is that it takes up 20% to 25% of the extra area to implement two SuperSpeed ​​data paths and two Hi-Speed ​​data paths, and requires two sets of phase-locked loop circuits. (PLL) and two sets of power, ground, and data pins. The end result is a system-owned High-Speed ​​data path that is one more than its actual needs.
A more efficient implementation is to use a physical layer that has been optimized for the USB Type-C specification. It has two SuperSpeed ​​data paths, a Hi-Speed ​​data path, and a set of phase locks. Loop circuit and a set of power, ground, and data pins.
Which implementation method designers choose depends on their end application. The cost-sensitive market will choose to save space and chips by eliminating an extra Hi-Speed ​​data path and reducing the number of pins by up to 40%.
USB Type-C signaling
The second challenge in implementing USB Type-C is the signal complexity required for 24-pin connectors. The USB Type-C specification clarifies the configuration of channel (CC) signals and power output (PD) signals to define various parameters, such as the direction of the connector, how much power can be carried by any wire plugged into the Type-C port, and what the connector is. The time is in the switching mode for audio and video.
Supporting the configuration of channel signals and power output signals simultaneously requires additional logic: power output message controllers and configuration channel logic. Part of the design challenge is dealing with two types of signals that can occur at different voltages, depending on the combination of signals at the time.
The Type-C specification also abandoned the USB On-The-Go concept and replaced it with the Dual Role Port concept. USB On-The-Go is a signaling method used to indicate whether a port is being used as a host or as a device. The On-The-Go protocol uses the ID pin to signal whether the port is the master or device at work; however, Type-C does not have this signal, so use the power output message signal to do the job, which makes the PD signal Achieve further complication.
Systematic problem
Type-C connectors make USB users' lives easier, but at the cost of making the designer's work more complicated. Designers will have to decide which one they want to support USB 2.0, 3.0, and/or 3.1, how to handle power output, and whether to support audio and video switchable modes.
The implementation of USB Type-C will also have a systemic impact. For example, if the SoC is intended to support power output functions, the designer can choose to use an external power management chip that meets all relevant safety conditions. This means splitting the power output and configuring the channel logic, perhaps split between the physical layer and a separate power management chip, or the main system CPU or even a dedicated external microcontroller.
Synopsys' comprehensive USB controller and physical layer IP portfolio has been successfully adopted by more than 3,000 USB designs and has been validated with approximately 3 billion shipped devices. This is an in-depth and straightforward design experience that enables us to develop USB 3.1 physical layer IP optimized for use with Type-C connectors, as well as support tools and verification environments necessary to implement Type-C functionality - this Make the designer's work easier.
Author: Synopsys USB PHY IP, senior product marketing manager Gervais Fong
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