Design and Implementation of Airborne TV Guided VGA/TV Converter

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Abstract : This paper introduces the basic characteristics and functions of AIT2138 digital video processor, realizes a video format conversion between standard VGA and non-standard video, and further completes a certain type of fighter VGA/TV in China. The software and hardware design experiment of the converter: Explain in detail the overall design of the video converter and some electromagnetic interference problems in the machine test and the electromagnetic compatibility problem in the power supply design, and propose a solution; introduce the software control flow of the video converter and The principle and process of automatic monitoring and processing of the input video signal format.
Keywords : AIT2138; video converter; electromagnetic compatibility; progressive scan; interlaced scanning

1 Introduction With the development of multimedia video technology, education, business presentation, game entertainment, video surveillance, airborne video display and other fields require the conversion of VGA video signals output by PC into standard TV signals suitable for ordinary TV. At present, most of VGA video uses progressive scanning technology, while analog TV signals use interlaced scanning technology. And the respective line frequency and field frequency are not the same, therefore, it is very necessary and urgent to design a special VGA/TV video converter. The basic principle of the VGA/TV video converter is to write the frame memory with a standard timing through the frame memory. The frame is read in another format and the scanning frequency is adjusted by increasing or decreasing the line field until a standard television signal format is formed.

Many aircraft in our country use PAL displays similar to color televisions. In the case where the display graphics resolution is not critical, these existing devices can be fully utilized as display terminals of the onboard computer. However, the display interface of a general computer does not directly support the team PAL system. Need to make the appropriate conversion between the VGA interface and the PAL system. In order to realize the conversion of the display controller VGA signal to the analog TV video signal, it is compatible with the display mode of the analog video of the multi-function display. The author designed a VGMTV video converter based on AIT2138. The video converter converts the universal VGA signal to a broadcast quality PAL video signal. Of course, the AIT2138's output also supports NTSC and S-Video video formats, but these two output formats are not considered in this article.

This paper introduces the function of AIT2138, gives the working principle and design idea of ​​VGA/TV video converter hardware system; introduces the system software design. Using the single-chip microcomputer to flexibly realize the programming control of the video conversion core AIT2138 with 12C bus, and research on the automatic monitoring and automatic processing methods of input various video signals.

2 How AIT2138 and hardware systems work
2.1 Main Functions of
AIT2138 The AIT2138 video converter processes analog R, G, and B signals of standard VGA and converts them into NrPSC or PAL video signals. The conversion of the scan frequency is done by means of an external frame memory. The AIT2138 converts 640x480 (85 Hz), 800x600 (75 Hzl, 1024x768 (60 Hz), 16.7 MHz true color images into NTPSC or PAL video signals. All video signals are digitally processed. The D/A converter uses super-sampling circuit technology to make the analog output filter very simple. The three output pins of the circuit can simultaneously combine and output composite video and S-Video (luminance and chroma separation), RGB or YCbCr signals. The AIT2138 supports the VESA DPMS energy saving mode, which can effectively reduce the power consumption of the system.

The internal functional block diagram of Arl2138 is shown in Figure 1.

Its characteristics are as follows:
(1) The same screen is displayed on PC/TV, plug and play, I2C control, no driver required:
(2) Support 256 Kxl6 bit EDO storage or 1 Mxl6 bit SDRAM:
(3) FIic-FreeTM anti-flicker filtering technology, support image freeze, enlarge and move.

2.2 Video Converter Hardware System
The VGA/TV video conversion card designed by the author is mainly composed of power circuit, video conversion circuit and video conversion control circuit. Its hardware system block diagram is shown in Figure 2.


The onboard power supply is 27V. To ensure system compatibility, the Vieor dedicated power module is used to convert the onboard power supply to the 5V pure system power supply, providing a reliable environment for the normal operation of the system.

The VGA signal output from the on-board display controller is input to the front end of the system, and is processed (shaped, etc.) into the AIT2138. The AIT2138 is based on the refresh rate of the input VGA signal. A frame VGA progressive scan video signal is A/D sampled, buffered and clamped. Cached in the external SDRAM, after the parity field recombination and data interpolation in the field, and then processed by D/A, converted to analog video signal at the output.

The control module of the system is implemented by AT89C51. The AIT2138 power-on initialization and internal register settings are accomplished using a general-purpose I/O analog FC bus.

2.3 Special considerations in system hardware design
2.3.1 Video front-end processing
VGA signal input The three 8-bit A/D converters of Arl"2138 can be used to perform MD conversion on each channel of R, G, and B signals at a sampling rate of 48 MHz. HSYNC and VSYNC are Schmitt trigger buffer. The conversion reference voltage of the A/D converter can be set by itself. The designed RGB signal level range is OV~O.85 V, and the given external reference voltage is VK, which cannot be lower than The maximum value of the RGB signal level. Digital video processing is performed using the YUV color component, so the input RGB signal is converted into the 4:2:2 format YUV component signal using the RGB-YUV matrix in the AIT2138. Each component has a length of 8 bits and the total output signal operates at 24 bits on the data bus. It is found in the experiment that the 5-wire anti-flicker finite impulse response digital filter inside the AIT2138 can effectively reduce the flicker of the output PAL TV signal. .

2.3.2 Setting the working mode The
AIT2138 has two modes: master and slave. The main mode is chosen in this design, in which the circuit generates all clock and sync signals and provides horizontal and vertical sync and internal pixel clocks to external memory devices. The multiplexed input, FIFO, and memory external to the circuit will strictly follow the synchronization signals and clocks provided by the AIT2138.

2.3.3 Digital Video Encoding
The core of AIT2138 is the processor part. Mainly used to read YUV digital video data in 4:2:2 format from an external storage device. Then the encoding process is performed. Since the input signal is divided into two signal components, luminance and chrominance, the chrominance signal is modulated by the composite digital subcarrier. Therefore, the luminance and chrominance signals can be interpolated twice as fast as the pixel rate. It is converted into an analog composite video signal by two 10-bit D/A converters, and then output through the third-channel 10-bit converter. Care must be taken to adjust the AIT2138 format control pin to select different clock parameters. Set the output of the video converter to the PAL standard TV signal output that is compatible with the onboard multifunction display.

3 system software design
3.1 I2C protocol implementation
I2C bus is a simple, bidirectional two-wire synchronous serial bus. It features a high-performance serial bus that includes bus arbitration and high- and low-speed device synchronization for multi-master systems. The devices on the I2C bus are connected by a serial data line SDA and a serial clock line SCL. Send information.

In this system, the I/0 pins 1 and 2 of the P4 port of the AT89C51 are used to simulate the SCL and SDA pins of the 12C bus, respectively. The AT89C51 acts as a master to send commands on the bus. The AIT2138 acts as a receiver to receive commands on the bus. As an important information for bus rulings. The address of the AIT2138 must be included in the send command, and its address is 88H. The F2C read flow of AIT2138 is shown in Figure 3.


The writing process of AIT2138 is relatively simple. No need to read and write after writing the device address. This is the second Start Condition that is forced into the above sequence. It should be noted that there is one clock pulse per bit of data transmitted on the I2C bus. The clock pulse here is not like the normal clock must be periodic, and its clock interval can be different. When the bus is in standby (ie, "non-busy" state), SDA and SCL must be held high, and SCL is clamped low when the I2C bus is turned off. Data transfer can only be initialized when the bus is in a "non-busy" state. During data transmission. As long as the clock line is high, the data lines must be stable. The level change on the data line is allowed only when the clock line is low. While the clock line is held high, the falling edge on the data line is the start signal, the rising edge is the stop signal, and the start and stop signals are generated by the host. The AIT2138 easily monitors these signals.

3.2 System software flow
Software design is a difficult point in the design of this system, in the first version of the system design. The AIT2138 automatically detects the VGA video signal at the input end to set the line and field sync frequency, synchronizes the internal video A/D conversion and the internal field and video conversion process of the external video buffer. During use, the image jitter on the onboard multifunction display was found. Moreover, the position of the display image is offset from the field of view of the multi-function display, which seriously affects the video effect.

The study found. The problem lies in the adaptive adjustment function of the AIT2138. It internally specifies several gears for the line and field sync signals of the VGA signal. Take field synchronization as an example, it is divided into 63 Hz-69 Hz, 69 Hz-73 Hz. 73 Hz - 79 Hz, 79 Hz ~ 85 Hz 4 gears, due to its internal automatic monitoring function is not perfect. Therefore, it is easy to classify a video signal with a refresh rate of 75 Hz into a gear of 69 Hz to 73 Hz, which easily causes jitter of the back-end analog video output. The offset of the backend video field of view is internal to the AIT2138. HPR is related to VPR. Therefore, the author proposes the following optimal control scheme. The software flow is shown in Figure 4.


The AT89C2051 first detects the presence or absence of a line sync signal on the converter input port. If so, continue to detect the presence or absence of the field sync signal. If not, it is judged as a 5-wire video signal, and when a 5-wire video signal is input. The line and field sync signals of the signal are directly connected to the AIT2138. Then set the time threshold of the line and field frequency counting by setting the values ​​of the two 16-bit timers in the AT89C2051. Counts the pulses appearing on the line and field sync signal lines of the two I/O pins of the AT89C2051 during the specified time interval. The exact line and field frequency can be obtained by calculating the ratio of the number of pulses to the time interval. After obtaining the line and field frequency, the specific parameters of the 5-wire video signal to be processed in the AIT12138 conversion process are optimized, including the interception position and area of ​​the progressive video image and the position of the interlaced TV image display. The AT12138 is then programmed via the FC interface.

4 system anti-interference design in the design process. Taking into account the adaptability of the equipment to the outside, the following measures are mainly taken: the casing is made of metal aluminum, the metal part of the casing is well grounded, and it has the function of protecting electromagnetic interference; in order to ensure long-term connection between the terminals of each component ground wire Connect reliably. The tinned copper lug is used. At the same time, the lug is screwed to the base to ensure good grounding for a long time, and the whole component is protected from moisture: the button panel is in good contact with the casing through the copper wire. Prevent external electromagnetic waves from interfering with the normal operation of the device; connect high and low frequency filter capacitors at the output end of the power supply to prevent the influence of high and low frequency noise on the components. Pay attention to the PCB design: digital ground and analog ground separation, apply EMI filter device to reduce VDDA power supply noise; LPF to AITl2138 overall circuit pin length should be less than 0.5 inches; VDDA and VSSA terminals should be connected to O. A 1μF bypass capacitor to reduce noise.

5 Conclusion This VGA/TV converter is characterized by the conversion of the video signal output by the progressive scan microcomputer. And can get broadcast TV-level PAL TV video signals. After a test flight on a certain type of fighter aircraft, the PAL standard TV video signal with good effect is obtained, which has high application value.

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