An embedded application system based on the domestic processor Godson 2F was designed, which is mainly for automotive and portable devices. For the characteristics of the car and portable devices, the low power consumption and stability are highlighted in the chip selection; the DC power supply is optimized to improve the efficiency of the whole system; in the debugging process of the system, the SM502 chip I2C is eliminated by an alternative means. The logical bug enables the system to support all types of memory modules on the market; in order to make the signal integrity of the system meet the requirements of high-frequency circuits, the corresponding design methods and processes are proposed.
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0. introduction
In recent years, car and portable multimedia playback devices have been highly sought after, and various designs have been launched. The automotive and portable device design based on the Godson 2F[1,2] (LOONGSON-2F) processor is targeted at high-performance, low-power embedded applications such as automotive entertainment, ultra-mobile devices (UMD), and mobile Internet devices (MID). A company engaged in development and production. The solution uses the Loongson 2F (LOONGSON-2F) processor as the control core. According to the working environment and characteristics of the vehicle and portable devices, the SM502 [3] multi-function display control chip can support multiple media formats, enabling Internet access and viewing. TV, recording and playing music; on-board FLASH and DDR2 memory, can independently guide the system kernel to work, using the serial port as the system terminal. It can also be extended by the on-board universal PCI and LOCAL BUS general route interface, which is convenient for users to carry out secondary development. In addition, the CPU uses domestic chips, which has low power consumption and low price. The design has high application and reference. value.
1. The function and features of Godson 2F processor
The Loongson 2F (LOONGSON-2F) processor used in this system is a universal RISC microprocessor with a 64-bit MIPSIII instruction set recently released by the Institute of Computing Technology of the Chinese Academy of Sciences. The processor is the first in China to adopt a 90nm CMOS design process with an area of ​​35nm2. The measured power consumption is 4"5W at a typical operating frequency of 800MHz, and the maximum operating frequency is up to 1G. The highest floating point operation speed is 40/8 billion times per second. Dual/single-precision floating-point operation, on-chip integration of IO controllers such as PCI/PCIX, and integration of on-chip secondary CACHE, DDR2 memory controllers, ideal for high-end embedded applications.
2. System hardware structure design
The structural framework of the system is shown in Figure 1.
The Loongson 2F (LOONGSON-2F) processor is the control center of the entire system and handles all data processing tasks. The system uses the ICS950220 clock synthesizer to generate the clock required for each chip on the motherboard, while the chip has a watchdog function. System memory is extended by the internal DDR2 controller integrated in the processor. Taking into account the PCB board area and the higher bandwidth requirements for memory access, four 16-bit wide memory granules are used. The memory capacity depends on the capacity of the granules. It can support up to 1GB of memory and its working frequency is 300MHz. The 512KB Flash ROM is extended by the LOCAL BUS provided by the processor for system BIOS storage.
2.1 system power supply
Both on-board and portable devices require DC power, so energy efficiency and efficiency are the subject of power supply design. As shown in the power module of Figure 1, the system board uses a +5V DC adapter as the power supply. The 1.2V supplied to the CPU and the 3.3V DC power supply used in the supply interface circuit are more efficient due to the relatively large current. Switching power supply. According to the conventional design, the 1.8V power supply used for DDR2 and SM502 is introduced by the 3.3V power supply and is generated by two linear power supplies (LDOs). The system is changed to a higher efficiency switching power supply, which improves the efficiency of the whole system. The power consumption of the entire system is measured to be within 10W.
2.2 System Interface
1. The system drives various interfaces through the multi-function display control chip SM502. The SM502 can be directly connected to the processor through the PCI BUS to support 2D display acceleration. It can provide: AC97 standard audio interface (controlled by ALC203 chip) and a UBS1.1 interface. A standard RS232 serial port and a debug serial port (all controlled by SP3232 chip), VGA and LCD display interface, ZV video interface (controlled by SSA7118 chip).
2. The system adopts RTL8139D as the Ethernet control chip through PCI BUS, and provides 10/100M Ethernet interface.
3. The system adopts uPD720102 as the USB controller chip through PCI BUS, and provides three USB2.0 interfaces. One of the USB interfaces provides an SD/MMC interface through the AU6331 reader controller chip.
3. system software
The system runs under the LINUX DEBIAN4.0 operating system and its kernel is LINUX 2.6.21. Bootoarder–PMON2000 is burned in the onboard BIOS ROM, and the initialization of the processor, cache, memory controller, and network controller is automatically completed after power-on. At the same time, PMON2000 has a small number of command sets for reading and writing memory, flashing on-board flash, IP settings, serial port settings, and data communication with the host, including uploading, downloading files, and receiving hosts. Release instructions and so on. The LINUX 2.6.21 kernel is loaded into memory via PMON2000's internal commands.
There is a ROM on the memory stick, which stores information such as memory size, row address number, column address number, and bank number of memory. This information can be accessed through the I2C bus. As a general design, it is required to support a variety of different types of memory modules. During the debugging process of the system, we found that the I2C logic of the SM502 chip has a bug. Therefore, the SM502's gpio is used to simulate the I2C timing to read the memory (DIMM) strip information. And using the read information to configure the DDR2 controller of the Godson 2F processor, and received good results. The system has been tested to support all types of memory modules on the market.
4. Signal integrity design
Since the entire system module circuit is small in size and the operating frequency of the circuit is high, the entire design has strict requirements on signal integrity. The Loongson 2F processor's DDR2 memory total channel operating frequency is up to 300MHz. This part of the circuit is a bottleneck in high-speed circuit design. The results of this part of the circuit simulation can basically reflect the effect of the entire circuit signal transmission. The DDR2 control signal is taken as an example to describe the design method and flow of the problem.
In the actual design, the IBIS model and simulation tool [4] of the Godson 2F are used to predetermine the routing topology and matching mode of the key signals, thereby establishing the constraints of the PCB layout. Firstly, the simulation model before PCB layout is extracted. By observing the corresponding simulation result waveform, the topology of the trace and the matching circuit parameters for obtaining better signal quality can be determined. After the PCB layout is completed, the actual topology is extracted and simulated. The extracted topology is shown in Figure 3. At this point the model has included the laminate and impedance control information for the PCB and modeled the actual vias. The final best trace can be obtained by adjusting the traces and observing the simulation results. Figure 4 shows the adjusted simulation results. It can be observed that the signal quality is better at the receiver end, and the overshoot of the driver is also within the acceptable range. Finally, the actual signal waveform is measured in the actual board debugging, and the matching of the matching components is performed to ensure the reliability of the actual signal quality. Practice has shown that this method and process can reduce the design risk caused by signal integrity and reduce the difficulty of debugging. All simulation IC modeling parameters in this document are typical, and the driver's excitation signal is a 133MHz periodic signal.
5. summary
This paper introduces the design process of the vehicle and portable equipment system based on the Godson 2F processor. It mainly describes the key technologies such as system hardware structure, software system, signal integrity design and improving the efficiency of the whole machine. The system is compact in structure and can work independently and provides a flexible expansion interface, which has great application prospects.
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